Content management system and markup test area

This page is NOT part of the documentation.

This sandbox is for markup testing. You can’t edit what you see in your browser here; you have to edit the markup file and run the CMS script to translate it.

Talk to Amy & Becky about <XML quoting>.

This paragraph contains an ASCII BEL (control-G). It’s available as a “macro spoiler,” because BEL is stripped from the HTML output as the very last processing step.

Here comes “Peter Cottentail,” and he’s coming down the bunny trail. Better get out of his way.

Time for a variable and a constant. Then “we recover” and “we rejoice” and think about goin’ home.

Here is bold italic?

Here are mono bold and bold mono and we haven’t segfaulted yet. They do what we hope.

Here are mono italic, italic mono, bold italic mono, and mono italic bold. They also do what we hope.

Here are some special symbols and their uses. First is a regular-dash. Next is a minus sign so that numbers like −12,345 are harmonized with their +12,345 counterparts. Then an en dash–sometimes useful, although the version for this font seems narrow to me. (No point complaining, because I’m sure it’s the advertised width of the letter n.) We wrap this up with—I know you’ve been waiting for this—the illustrious em dash. These are all accessed via the character sequences -, ~, --, and --- respectively.

Here is a spacing experiment with monospace 1 and monospace 3. Nope, any number of spaces in monospace becomes one space. Sorry.

Heading spacing

This is a basic paragraph under a heading, just as a test.

I decree that 80 columns of preformatted text must fit. Like this:

0        1         2         3         4         5         6         7         8
12345678901234567890123456789012345678901234567890123456789012345678901234567890

Original lyrics

I would like to write a poem,
but I don't know how to rhyme.
And of rhymes I ought to know 'em,
but I'm running out of time.

Extended lyrics

I would like to write a poem,
but I don't know how to rhyme.
And of rhymes I ought to know 'em,
but I'm running out of time.

I know this song is bad,
but it needs another verse.
And to keep from getting mad,
I will have to keep it terse.

Aside

You just saw a third-level heading.

Link to https://wright.edu is up.

Link to my institution is up.

Link to my institution is up. Also see https://wright.edu.

It’s Wednesday. At least it was.

Don’t forget to include a Blauug!

Paragraph spacing study

The architecture is intrinsically immune to certain memory exploits. A complete absence of DRAM eliminates the RowHammer class of leaky-capacitor exploits, and may also reduce susceptibility to radiation upsets. Absence of cache memory and speculative execution also rules out Spectre- and Meltdown-type attacks and reduces the range of side channel attacks that may be possible.

The firmware as written has no opcode that can result in data exchange between the stack and registers. Figure 8.6 does not suggest firmware modifications that could read data from the stack, short of having to pass through the code RAM. There are two electrical routes to write to stack memory, which would require complicit firmware using an elaborate control decoder scheme. The shorter route passes through via ff a, ff t, and ff c.

In the presence of well-behaved firmware, the only access to stack memory is via the CALL, RETURN, and privileged CALI instructions. No privilege escalation can result from stack overflow, and there is no possibility for stack underflow by programs that the program loader initializes correctly.

It is not possible to branch to locations in code memory that are not already present in a branch instruction in code memory. This allows exclusive ownership of portions of code memory by various users, along with arbitrary sharing of code memory as may be supported and permitted by the operating system.

Unprivileged users employ paged virtual memory for data segregation.

The I/O controller’s buffer memory and finite state machine memory will be electrically segregated on a per-serial-bus (meaning per-peripheral) basis.

Although memory hygiene for software is a hot topic today [NSA22], my architecture offers nothing new in this domain. I generally think that memory hygiene within a program is a long-solved problem for well-written applications.

Mingling of preformatted text with paragraphs

Below, the MHL5 (multiply high and low with tribble 5) instruction multiplies each of the six 6-bit tribbles of b with tribble 5 (most significant tribble) of a. These six multiplications each produce a 12-bit result, which is split into two halves across the left and right copies of register m.

m = b mhl5 a

This next line adds m to c, but it’s important to remember that MHL5 intentionally “desynchronized” the left and right copies of m. Because in this addition m is the left operand, it is the uppermost 6 bits of each of the six multiplications that is being added to c.

c = m + c

DSL (double shift left) is a key instruction for long multiplication, providing in one CPU instruction what would otherwise take five instructions. In the line below, DSL adds the T(emporal) flag with wrapping to d, and then shifts the sum left six bits. The six bits shifted in on the right come from the six leftmost bits of c. The result is written to d.

d = c dsl d

The below LSL (logical shift left) shifts c left by six bit positions. Logical shifts are not construed to overflow in this architecture. Note that six copies of the octal amount to shift must be provided, because 6 alpha RAMs and 6 gamma RAMs participate in the operation.

c = c lsl 060606060606`o

We again add m to c, except this time m is the right operand, so it’s the lowermost 6 bits of the six MHL5 multiplication that gets picked up. Carry may occur.

c = c + m

In the final line, we add the carry bit to d. Note that in Dauug|36 syntax, ++ means “add twice” as opposed to “increment.” These “two additions” – adding 0, and adding the carry bit – are merely conceptual and are done in a single pass through the ALU, meaning that only one instruction is needed.

d = d ++ 0

Quick links

Examples include 36-bit multiplication, Preemptive multitasking, and Architecture.