Dauug|36 terminology

Below are some terms used in this documentation, as well as in the architecture. I’ve spelled out some common abbreviations for clarity, and I occasionally use vocabulary from [1]. This list is a work in progress.

ALU. Arithmetic logic unit.

ALU operation. A computation task executed by one specific arithmetic logic unit SRAM or layer during the execution of an instruction.

Arithmetic shift. Multiplication or division by a power of two, rounding towards negative infinity in the case of division. (This is not the customary definition.)

Buyer. An authority responsible for the selection, procurement, installation, operation, and security of a computing platform on behalf of a risk owner.

Call stack. In Dauug|36 minicomputers, a 255-deep stack of 36-bit values that are accessed primarily via CALL and RETURN instructions. Each 36-bit value includes a 27-bit address of the instruction following CALL (also called the return address), a copy of the 4 CPU flag bits at the time CALL was executed (these being the Negative, Zero, Temporal, and Range flags), and 5 unused bits.

Although the call stack contains CPU flags as of the time of a CALL, the RETURN instruction does not restore these flags to their earlier value. A different instruction, REVERT, can be used in place of RETURN and restores the flags.

Dauug|36 call stacks do not provide addressable memory and do not contain local variables or other data except for return addresses and CPU flags. These stacks cannot be made deeper than 255 values, and they are not intended to support recursion directly.

See also return address stack.

Chapter 8 minicomputer. A fully-simulated minicomputer in Dauug|36 minicomputers, but still lacking multitasking, firmware loading, and I/O. Chapters 1 through 8 of Marc’s dissertation describe the minicomputer through this level of completion.

Click. The enumerated position of a clock cycle within a CPU cycle. Dauug|36 minicomputers use four clicks, numbered click 0 through click 3.

Clock cycle. The span of time between two consecutive rising edges of the system clock oscillator.

Code RAM. In Dauug|36 minicomputers, one or more primary storage SRAMs that contain instructions that are fetched and executed by the CPU.

Complex logic. Digital electronic parts that, because of their complexity, may contain unseen exploitable defects.

CPU cycle. The amortized span of clock cycles required to execute a CPU instruction. In Dauug|36 minicomputers, a CPU cycle is four clock cycles.

Data RAM. In Dauug|36 minicomputers, one or more primary storage SRAMs that are read or written by load or store instructions.

Direct memory. Memory where the location being accessed is beyond a program’s dynamic control, such as a register specified in a CPU instruction.

Discounted logic. Digital electronic parts that are unlikely to contain exploitable defects, as evidenced in a written assessment or other approved measure.

Family. In Dauug|36 minicomputers, a group of opcodes that have the same purpose but need different control signals due to minor variations.

Firmware loader. Circuit that cold-boots a minicomputer, including logic that copies firmware from nonvolatile storage to SRAM logic elements and code memory.

FSM. Finite state machine.

Indirect memory. Memory where a program dynamically controls which location is accessed, such as data memory accessed via a register-specified address.

Instruction. In Dauug|36 minicomputers, a 36-bit word in code memory consisting of an opcode with zero, one, two, or three operands.

Internal firewall. A boundary that isolates a portion of circuitry that is not solder-defined, such that exploits of defects within that portion cannot escape.

LFSR. Linear feedback shift register in Galois configuration.

Logical shift. A binary shift without any intent to multiply or divide. Unlike arithmetic shift, no overflow check is made.

Macro. In Dauug|36 minicomputers, one or more CPU instructions that to a programmer appears to be written as a single assembler instruction.

Maker-scale assembly tools. Capital equipment for electronics assembly that can be made available to most technically knowledgeable builders.

MEMS oscillator. A frequency synthesizer IC referenced to an on-die micro-electromechanical system (MEMS) resonator. Their displacement of crystal oscillators raises security concerns.

Mibit. 2²⁰ = 1,048,576 bits. In contrast, 1 Mbit is 1,000,000 bits.

Microcomputer. According to custom and [2], a “computer system that utilizes a microprocessor as its central control and arithmetic element.”

Microprocessor. A die that contains at least one complete CPU.

Minicomputer. A computer wherein all hardware logic that may contain exploitable defects is solder-defined, and all firmware is open-source.

Net. An electrically contiguous set of component pins. A net may communicate one bit at a time among electrical components.

Node. An intentional grouping of related nets. A node may communicate many bits, such as a word, at a time among electrical components.

Nonprivileged program. A program that contains no privileged instructions. Also called a user program.

NPRIV mode. A condition where the 8-bit user identifier is employed without modification, and the preemption timer for multitasking is permitted to run. This is the natural condition of user programs, as well as an occasional condition of operating system code. Alternatives to NPRIV mode are PRIV mode and SETUP mode.

Opcode. In Dauug|36 minicomputers, a nine-bit field in a CPU instruction that the control decoder uses to define and execute the instruction.

Operand. In Dauug|36 minicomputers, a field of an instruction containing a 9-bit register number, 18-bit integer constant, or 27-bit code address.

Operation. In Dauug|36 minicomputers, a computation task executed by one specific ALU SRAM or layer during the execution of an instruction.

Overrange. A convenient synonym for out-of-range. In this architecture, this word does not mean to distinguish between overflow and underflow.

Primary storage. Non-cache memory that is accessible to or contains individual CPU instructions. Ordinarily termed “RAM” outside this architecture.

PRIV mode. A condition where the 8-bit user identifier is forced to read as all zeros, regardless of the identifier’s actual value. The preemption timer for multitasking is disabled. This is the natural condition of the superuser. Alternatives to PRIV mode are NPRIV mode and SETUP mode.

Privileged program. A program that contains at least one privileged instruction. In Dauug|36 minicomputers, an operating system precludes unauthorized use of privileges by (i) requiring authorization before loading a privileged program into code memory, and (ii) requiring authorization before executing a privileged program that is already in code memory.

Aside. There is slightly more to this, because a program may include (with authorization) a branch to code that is within another program residing in code memory.

PRNG. Pseudorandom number generator.

Program loader. Operating system code that copies a program to code memory, excludes forbidden privileged instructions, and completes link editing.

RAM. Within this architecture, an informal abbreviation for SRAM. There is no DRAM in this architecture.

Reserved. Unallocated. This term appears in a few tables in the dissertation where a resource is present, but no purpose or implementation is present as yet.

Return address stack. A synonym for call stack. I don’t really like having employed two terms for the same thing here, but the advantage to the term “return address stack” is the implication that it only contains return addresses. (The fact it happens to also store CPU flags is irrelevant in cases where the RETURN instruction, which ignores these flags, is used at the end of a CALL.)

See also call stack.

SETUP mode. A condition where the 8-bit user identifier is forced to read as all zeros for the register file only, regardless of the identifier’s actual value, but the user identifier is employed without modification for the call stack and page table. SETUP mode is entered on occasion by the superuser to configure a user’s call stack and page table. Alternatives to SETUP mode are NPRIV mode and PRIV mode.

SPN. Substitution-permutation network.

SRAM. Static RAM. Most SRAM in this architecture implements logic using read-only lookup tables. A few SRAMs provide read-write storage.

Solder-defined behavior. Intentional operational characteristics of solder-defined hardware when used with exclusively open-source firmware.

Solder-defined hardware. Digital electronics needing only maker-scale assembly tools to build, in which all complex logic components are discounted.

Superuser. A program that is running as user 0; that is, all 8 identifier bits are zeros. This program is generally the principal core of the operating system.

Aside. I am unaware of any existing Dauug|36 operating systems that have a “root user” in the UNIX sense. In Dauug|36 minicomputers, the term superuser is unlikely to refer to a person, an account, escalated command shell privileges, or the like. Rather, the superuser is software that is situated (due solely to having all 8 identifier bits zero) to take advantage of many privileged instructions.

Supply-chain firewall. A preventive control that protects a buyer from unwanted procurement of exploitable defects via the buyer’s supply chain.

Support (verb). To be used in something’s implementation. The statement “ γ.pit supports PIT” means that  γ.pit is a part of PIT’s implementation.

Tribble. A six-bit subword of a 36-bit word. This word envisions a “tri-nibble,” a nibble that has been enlarged to the next multiple of three. It may also be a good companion for tetrade, an archaic term for a four-bit quantity.

User.

1. A resource user of the CPU; specifically, a running program.
2. A running program that is not the superuser.
3. An 8-bit identifier used to segregate data belonging to different running programs.

User mode. This is a synonym for NPRIV mode.

User program. This is a synonym for nonprivileged program.

Word. A bit vector of a CPU architecture’s natural size. In this architecture, the architecture’s natural size is 36 bits for both code and data.

References

[1] International Organization for Standardization. 2018. ISO/IEC 27000:2018(E). Information technology—Security techniques—Information security management systems—Overview and vocabulary. Retrieved 14 July 2020 from https://standards.iso.org/ittf/PubliclyAvailableStandards/c073906_ISO_IEC_27000_2018_E.zip

[2] Andrew Butterfield, Gerard Ekembe Ngondi, and Anne Kerr, eds. 2016. A Dictionary of Computer Science (7th ed.). Oxford University Press, Oxford, England.